The present invention relates to a TAP (Test Access Port) controller used in testing an IC chip made based on IEEE 1149.1 of the U.S. IEEE standard.
A boundary scan system defined in the IEEE standard 1149.1 for testing a digital IC chip comprises a boundary scan register provided between an internal logic circuit and an I/O terminal for entering each test signal and a TAP controller for feeding various test signals to this boundary scan register.
The TAP controller allows a test mode selector signal (TMS) and a test clock (TCK) to be entered while allowing sixteen kinds of test signals to be emitted. FIG. 1 illustrates a block diagram of a conventional TAP controller 70 which is connected to a boundary scan register cell 71 for entering the test signal. An asterisk sign (*) is attached to the end of the name of the active low signal.
From the exterior to the TAP controller 70, a test clock TCK signal 12 and a TMS signal 44 of the mode selector signal are entered, while, from the TAP controller 70 to the boundary scan register cell 71, a ShiftDR (shift data register) signal 41 and a ClockDR (clock data register) signal 42 are emitted. A further input/output signal 73 is independent of the boundary scan register 71.
FIG. 2 illustrates an internal circuit of the boundary scan register cell. An external input PI (pin-in) signal 72 is entered from an input pin to the boundary scan register cell 71, and, as the shift input of the previous stage boundary register cell (not shown), a SO (shift-out) signal 75 is emitted.
A selector circuit (MPX) 81 selects the PI signal 72, with a ShiftDR signal 41 as the selector signal, when this ShiftDR signal 41 is low, and selects an SI signal 74 when it is high. A signal 82 selected by this selector circuit 81 is entered to a DFF (D-type flip-flop) 83 to be emitted as the SO signal 75 at the rising edge of the ClockDR signal 42.
A circuit diagram of a conventional TAP controller 70 is shown in FIGS. 3 and 4 in more detail. For the purpose of illustration, the TAP controller 70 is divided into two portions 70A and 70B. The TAP controller 70 comprises DFF 4 to 7 for emitting a set rising edge, DFF 27 to 29 and 32 for emitting a reset rising edge, inverters 2, 13 and 45, NAND gates 22 to 24, 30, 33 and 46 to 66 and AND gates 31, 34, and enters a TRST* (TAP reset) signal 1, a TCK signal 12 and a TMS signal 44 while emitting a Reset signal 35, a Select signal 36, Enable signal 37, ShiftIR (Shift Instruction register) signal 38, ClockIR signal 39, UpdateIR signal 40, ShiftDR signal 41, ClockDR signal 42 and UpdateDR signal 43, respectively. NA signal 8 through ND signal 11, A to D signals 21 to 18, A* to D* signals 17 to 14 are internal signals.
As described above, the TAP controller 70 is shown divided into FIGS. 3 and 4, and the portions 8, 9, 10 and 11 in FIG. 3 are connected to 8, 9, 10 and 11 in FIG. 4, respectively, and each internal signal is connected to a corresponding one having the same name and numeral as that of FIGS. 3 and 4, and TRST*, TCK TMS signals 1, 12 and 44 are entered and the output signals 35 through 43 are each emitted as test signals.
The timing of the signals in the conventional TAP controller 70 and the boundary scan register cell 71 are shown in FIG. 5. Referring to the control timing of this TAP controller 70, since, with its normal operating condition free of the test operation (Test-Logic-Reset condition as shown in IEEE 1149.1), ShiftDR signal 41 is low, selector circuit 81 of FIG. 2 selects a PI signal 72, which, if it lies on the intermediate potential level, induces a penetrating current at the selector circuit 81 or DFF 83.
In the above-described method of controlling the conventional TAP controller 70, since, with the Test-Logic-Reset condition, ShiftDR signal 41 is low, and the selector circuit 81 selects the PI signal 72, when the PI signal 72 is on the intermediate level of potential, the penetrating current can be induced at the selector circuit 81 or DFF 83.